IC 74138 PDF

Lead Small Outline Integrated Circuit (SOIC), JEDEC MS, Narrow. DM74LSSJ. M16D. Lead Small Outline Package (SOP), EIAJ TYPE II. A. ACTIVE. LCCC. FK. 1. TBD. POST-PLATE. N / A for Pkg Type. – 55 to A. SNJ54LS. FK. EA. ACTIVE. 74LS is a high speed 1-of-8 Decoder/ Demultiplexer. Shop/Components & Parts/IC’s/74 SERIES/74LS HD74LSP 3 to 8 Decoder/Demultiplexer.

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Logic IC 74138

All of its essential components and connections are illustrated by graphic symbols arranged to describe operations as clearly as possible but without regard ci the physical form of the various items, components or connections. A line decoder can be implemented without external inverters and a line decoder 741138 only one inverter.

For understanding the working of device let us construct a simple application circuit with a few external components as shown below. Also the chip inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. Select options Learn More.

Choose an option 3.

Submitted by admin on 26 October After connecting the enable pins as shown in circuit diagram you can use the input line to get the output. Product successfully added to your wishlist! You must be logged in to leave a review.

The memory unit data exchange rate determines the performance of any application and the delays of any kind are not tolerable there. The design is also made for the chip to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high performance memory systems these decoders can be used to minimize the effects of system decoding.

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This device is ideally suited for high speed bipolar memory chip select address decoding. This amplifier exhibit low supply-current drain and input bias and offset currents that is much less than that of the LM Standard frequency crystals — use these crystals to provide a clock input to your microprocessor. TL — Programmable Reference Voltage. As mentioned earlier the chip is specifically designed to be used in high-performance memory-decoding or data-routing applications which require very short propagation delay times.

Features 74ls features include; Designed Specifically for High-Speed: Reviews 0 Leave A Review You must be logged in to leave a review.

How to use 74LS Decoder For understanding the working of device let us construct a simple application circuit with a few external components as shown below. Product already added to wishlist! Description Resources Learn Videos Blog 74ls Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times.

In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. A line decoder can be implemented with no external inverters, and a line decoder requires only one inverter.

The three buttons here represent three input lines for the device.

The three enable pins of chip in which Two active-low and one active-high reduce the need for external gates or inverters when expanding. In such applications using 74LS line decoder is ideal because the delay times of this device are less than the typical access time of the memory.

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Drivers Motors Relay Servos Arduino. Choose an option 20 28 These devices contain four independent 2-input AND gates. This means that the effective system delay introduced by the decoder is negligible to affect the performance. For understanding the working let us consider the truth table of the device.

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The LM is a quadruple, independent, high-gain, internally compensated operational amplifiers designed to have operating characteristics similar to the LM The chip is designed for decoding or de-multiplexing applications and comes with 3 inputs to 8 output setup.

As shown in table first three rows the enable pins needed to be connected appropriately or irrespective of input lines all outputs will be high. Add to cart 47138 More. Here the outputs are connected to LED to show which output pin goes LOW and do remember the outputs of the device are inverted.

Features and Electrical characteristics of 74LS Decoder Designed specifically for high iv Incorporates three enable pins to simplify cascading De-multiplexing capability Schottky 774138 for high performance ESD protection Balanced propagation delays Inputs accept voltages higher than VCC Supply voltage: This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC.

All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design.

Wiring Diagram Third Level. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible.